湖北芯擎科技有限公司

Job Description:

1、SOC Design-For-Debug &Test methodology and micro architecture development.

2、ARM CoreSight micro architecture development and debug subsystem design and verification.

3、High performance and real-time cross-trigger engine design and verification for multi-core SOC.

4、Test-controller design and verification for PLL, MIPI, PCIE, USB3, DDR Debug and test.

5、Co-work with DFT team for SOC debug/test logic design and verification.

Job Description:

1、SOC Design-For-Debug &Test methodology and micro architecture development.

2、ARM CoreSight micro architecture development and debug subsystem design and verification.

3、High performance and real-time cross-trigger engine design and verification for multi-core SOC.

4、Test-controller design and verification for PLL, MIPI, PCIE, USB3, DDR Debug and test.

5、Co-work with DFT team for SOC debug/test logic design and verification.

Job Description:

1、SOC Design-For-Debug &Test methodology and micro architecture development.

2、ARM CoreSight micro architecture development and debug subsystem design and verification.

3、High performance and real-time cross-trigger engine design and verification for multi-core SOC.

4、Test-controller design and verification for PLL, MIPI, PCIE, USB3, DDR Debug and test.

5、Co-work with DFT team for SOC debug/test logic design and verification.

Job Description:

As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to:

1、Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc.

2、Bring up the virtual platform and analysis the performance and power simulation result.

3、Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem.

4、Work out the highly configurable work load model for the various components in various scenarios.

5、Work out the SoC use case and performance goal in system level with help from product engineer.

6、Assist design engineer to work out the ASIC micro-architecture.

7、Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models.

Job Description:

As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to:

1、Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc.

2、Bring up the virtual platform and analysis the performance and power simulation result.

3、Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem.

4、Work out the highly configurable work load model for the various components in various scenarios.

5、Work out the SoC use case and performance goal in system level with help from product engineer.

6、Assist design engineer to work out the ASIC micro-architecture.

7、Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models.

Job Description:

As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to:

1、Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc.

2、Bring up the virtual platform and analysis the performance and power simulation result.

3、Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem.

4、Work out the highly configurable work load model for the various components in various scenarios.

5、Work out the SoC use case and performance goal in system level with help from product engineer.

6、Assist design engineer to work out the ASIC micro-architecture.

7、Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models.

Job Description:

1、Responsible for Front-End chip implementation work from RTL2Netlist, including SOC/IP level Synthesis/STA/Formality check/Lint/CDC/Quality check.

2、Responsible for ASIC design methodology and flow development & optimization, interfacing with EDA vendors on technology.

3、Support Lint/CDC check, SDC/UPF writing.

4、Deliver constraints and closely co-work timing & power closure with P&R.

Job Description:

1、Responsible for Front-End chip implementation work from RTL2Netlist, including SOC/IP level Synthesis/STA/Formality check/Lint/CDC/Quality check.

2、Responsible for ASIC design methodology and flow development & optimization, interfacing with EDA vendors on technology.

3、Support Lint/CDC check, SDC/UPF writing.

4、Deliver constraints and closely co-work timing & power closure with P&R.

Job Description:

1、Responsible for Front-End chip implementation work from RTL2Netlist, including SOC/IP level Synthesis/STA/Formality check/Lint/CDC/Quality check.

2、Responsible for ASIC design methodology and flow development & optimization, interfacing with EDA vendors on technology.

3、Support Lint/CDC check, SDC/UPF writing.

4、Deliver constraints and closely co-work timing & power closure with P&R.

Job Description:

Lead or co-lead the team to achieve verification target of state-of-the-art ARM based SoC, or one of its sub-system. Be responsible for verification quality and schedule.

1、Lead the verification process, decompose tasks for each team member.

2、Create verifcation plan and review with architecture/design team.

3、Create random constraint test bench based on the requirement.

4、Create random test cases and direct test cases to achieve coverage goals.

5、Work closely with architecture/design team to identify problems.

6、Low-power verification.

7、Performance verification.

8、Finish verification tasks on time.

Job Description:

Lead or co-lead the team to achieve verification target of state-of-the-art ARM based SoC, or one of its sub-system. Be responsible for verification quality and schedule.

1、Lead the verification process, decompose tasks for each team member.

2、Create verifcation plan and review with architecture/design team.

3、Create random constraint test bench based on the requirement.

4、Create random test cases and direct test cases to achieve coverage goals.

5、Work closely with architecture/design team to identify problems.

6、Low-power verification.

7、Performance verification.

8、Finish verification tasks on time.

Job Description:

Lead or co-lead the team to achieve verification target of state-of-the-art ARM based SoC, or one of its sub-system. Be responsible for verification quality and schedule.

1、Lead the verification process, decompose tasks for each team member.

2、Create verifcation plan and review with architecture/design team.

3、Create random constraint test bench based on the requirement.

4、Create random test cases and direct test cases to achieve coverage goals.

5、Work closely with architecture/design team to identify problems.

6、Low-power verification.

7、Performance verification.

8、Finish verification tasks on time.

Job Description:

This position is for a digital-MCU design engineer to build next-gen automotive MCU chipsets.As part of the MCU design team, the design engineer will mainly focus on following areas, but not limited to:

1、Prepare micro-architecture specification for IP or subsystem design.

2、Provide detailed technical documentation with specifications, block diagrams, and requirements to stakeholders.

3、RTL coding to verify against circuit implementation; Perform integration into MCUs.

4、Module level Automotive functional safety related design and document.

5、Maintain the 3rd party IP from vendor and verify functions by creating test cases.

6、Module level synthesize with sdc/upf; support chip level synthesis as IP owner.

7、Assist with chip bring up and perform silicon/FPGA functional/performance validation.

8、Assist with automotive functional safety (ISO26262) certification.

9、Define timing and power specifications and identify timing solutions.

10、Assist with backend team on perform place-and-route and timing analysis of modules.

Job Description:

This position is for a digital-MCU design engineer to build next-gen automotive MCU chipsets.As part of the MCU design team, the design engineer will mainly focus on following areas, but not limited to:

1、Prepare micro-architecture specification for IP or subsystem design.

2、Provide detailed technical documentation with specifications, block diagrams, and requirements to stakeholders.

3、RTL coding to verify against circuit implementation; Perform integration into MCUs.

4、Module level Automotive functional safety related design and document.

5、Maintain the 3rd party IP from vendor and verify functions by creating test cases.

6、Module level synthesize with sdc/upf; support chip level synthesis as IP owner.

7、Assist with chip bring up and perform silicon/FPGA functional/performance validation.

8、Assist with automotive functional safety (ISO26262) certification.

9、Define timing and power specifications and identify timing solutions.

10、Assist with backend team on perform place-and-route and timing analysis of modules.

Job Description:

This position is for a digital-MCU design engineer to build next-gen automotive MCU chipsets.As part of the MCU design team, the design engineer will mainly focus on following areas, but not limited to:

1、Prepare micro-architecture specification for IP or subsystem design.

2、Provide detailed technical documentation with specifications, block diagrams, and requirements to stakeholders.

3、RTL coding to verify against circuit implementation; Perform integration into MCUs.

4、Module level Automotive functional safety related design and document.

5、Maintain the 3rd party IP from vendor and verify functions by creating test cases.

6、Module level synthesize with sdc/upf; support chip level synthesis as IP owner.

7、Assist with chip bring up and perform silicon/FPGA functional/performance validation.

8、Assist with automotive functional safety (ISO26262) certification.

9、Define timing and power specifications and identify timing solutions.

10、Assist with backend team on perform place-and-route and timing analysis of modules.